M5M5V208AKV-70L 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M5V208AKV-70L Datasheet PDF : 8 Pages
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Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
(4) TIMING DIAGRAMS
Read cycle
A0~17
S1
(Note 3)
S2
(Note 3)
OE
(Note 3)
DQ1~8
W = "H" level
Write cycle (W control mode)
A0~17
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tCW
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
(Note 3)
S1
S2
OE
W
DQ1~8
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten(OE)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
(Note 3)
(Note 3)
MITSUBISHI ELECTRIC
5
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