MCP6S93 查看數據表（PDF） - Microchip Technology

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MCP6S93

Single-Ended, Rail-to-Rail I/O, Low-Gain PGA

Microchip Technology 

MCP6S91/2/3

CS

SCK

tCSSC

tHI tLO

tSU tHD

1/fSCK

tCSH

tSCCS tCS1

tCS0

SI

tDO

tSOZ

SO

(first 16 bits out are always zeros)

FIGURE 1-5:

Detailed SPI™ Serial Interface Timing; SPI 1,1 Mode.

1.1 DC Output Voltage Specs / Model

1.1.1 IDEAL MODEL

The ideal PGA output voltage (VOUT) is:

EQUATION 1-1:

VO_ID = GVIN VREF = VSS = 0V

Where:

G is the nominal gain

(see Figure 1-6). This equation holds when there are

no gain or offset errors and when the VREF pin is tied to

a low-impedance source (<< 0.1Ω) at ground potential

(VSS = 0V).

1.1.2 LINEAR MODEL

The PGA’s linear region of operation, including offset

and gain errors, is modeled by the line VO_LIN shown in

Figure 1-6.

The end points of this line are at VO_ID = 0.3V and

VDD – 0.3V. Figure 1-6 shows the relationship between

the gain and offset specifications referred to in the

electrical specifications as follows:

EQUATION 1-3:

gE

=

100

%

----------V----2----–-----V----1----------

G(VDD – 0.6V)

VOS

=

----------V----1----------

G(1 + gE)

G = +1

The DC Gain Drift (∆G/∆TA) can be calculated from the

change in gE across temperature. This is shown in the

following equation:

EQUATION 1-4:

∆G ⁄ ∆TA

=

-∆---g----E-

∆TA

EQUATION 1-2:

VO_LIN

=

G(1

+

gE ) VI N

–

0----.-3---V--

G

+

VOS

+ 0.3V

VREF = VSS = 0V

 2004 Microchip Technology Inc.

DS21908A-page 8

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