D80C187-12 查看數據表（PDF） - Intel

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D80C187-12

80-BIT MATH COPROCESSOR

Intel 

80C187

ES is set if any unmasked exception bit is set cleared otherwise

See Table 2 for interpretation of condition code

TOP values

000 e Register 0 is Top of Stack

001 e Register 1 is Top of Stack







111 e Register 7 is Top of Stack

For definitions of exceptions refer to the section entitled

‘‘Exception Handling’’

Figure 4 Status Word

270640 – 3

6

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