K4B4G1646Q 查看數據表（PDF） - Samsung
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K4B4G1646Q Datasheet PDF : 65 Pages
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K4B4G1646Q
datasheet
Preliminary Rev. 0.5
DDR3L SDRAM
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in Table 20 and Figure 5.
[ Table 20 ] Single-ended output slew rate definition
Description
Measured
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
Defined by
[VOH(AC)-VOL(AC)] / Delta TRse
[VOH(AC)-VOL(AC)] / Delta TFse
[ Table 21 ] Single-ended output slew rate
Parameter
Symbol
Operation
Voltage
DDR3-800
Min Max
DDR3-1066
Min Max
DDR3-1333
Min Max
DDR3-1600
Min Max
Units
Single ended output slew rate
SRQse
1.35V
1.5V
1.75
51)
1.75
51)
1.75
51)
1.75
51)
V/ns
2.5
5
2.5
5
2.5
5
2.5
5
V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in
the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining
DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 5. Single-ended Output Slew Rate Definition
- 19 -
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