TH58NVG5S0FTA20 查看數據表（PDF） - Toshiba

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TH58NVG5S0FTA20

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

BLOCK DIAGRAM

I/O1

to

I/O8

CE 1

CLE

ALE

WE

RE

WP

PSL

RY / BY 1

CE 2

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20

I/O

Control circuit

(Chip A, B)

Status register

Address register

Command register

Logic control

Control circuit

VCC VSS

Column buffer

Column decoder

Data register

Sense amp

Memory cell array

RY / BY

I/O

Control circuit

HV generator

Status register

Address register

Command register

Logic control

Control circuit

Column buffer

Column decoder

Data register

Sense amp

Memory cell array

RY / BY 2

RY / BY

HV generator

(Chip C, D)

VCC VSS

3

2010-12-13C

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