PI74LCX16543 查看數據表（PDF） - Pericom Semiconductor

零件编号

产品描述 (功能)

生产厂家

PI74LCX16543

Fast CMOS 16-Bit Latched Transceivers

Pericom Semiconductor 

PI74LCX16543

1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122

Fast CMOS 16-Bit Latched Transceivers

Product Features

• Functionally compatible with FCT3, LVT, and 74 series

16543 families of products

• Tri-State outputs

• 5V Tolerant inputs and outputs

• 2.0V-3.6V VCC supply operation

• Balanced sink and source output drives (24 mA)

• Low ground bounce outputs

• Power down High impedance inputs and outputs

• Supports live insertion

• ESD Protection exceeds 2000V, Human Body Model

200V, Machine Model

• Packages available:

– 56-pin 240-mil wide plastic TSSOP (A)

– 56-pin 300-mil wide plastic SSOP (V)

Product Description

Pericom Semiconductor’s PI74LCX series of logic circuits are

produced using the Company’s advanced 0.6 micron CMOS

technology achieving high speed while maintaining low power

operation.

The PI74LCX16543 is 16-bit latched transceivers organized with two

sets of eight D-type latches with separate input and output controls

for each set. For data flow from A to B, for example, the A-to-B Enable

(xCEAB) input must be LOW in order to enter data from xAx or to take

data from xBx, as indicated in the Truth Table. With xCEAB LOW,

a LOW signal makes the A-to-B latches transparent; a subsequent

LOW-to-HIGH transition of the xLEAB signal puts the A latches in

the storage mode and their outputs no longer change the A inputs.

With xCEAB and xOEAB both LOW, the 3-state B output buffers are

active and reflect the data present at the output of the A latches.

Control of data from B to A is similar, but uses the xCEAB, xLEAB,

and xOEAB inputs.

The PI74LCX16543 can be driven from either 3.3V or 5.0V devices

allowing this device to be used as a translator in a mixed

3.3V/5.0V system.

Logic Block Diagram

1OEBA

1CEBA

1LEBA

1OEAB

1CEAB

1LEAB

C

1A0

D

C

D

TO 7 OTHER CHANNELS

2OEBA

2CEBA

2LEBA

2OEAB

2CEAB

2LEAB

1B0

2A0

C

2B0

D

C

D

TO 7 OTHER CHANNELS

1

PS2092B 09/19/02

Share Link: