UT62256CSCL-35L 查看數據表（PDF） - Utron Technology Inc
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UT62256CSCL-35L Datasheet PDF : 12 Pages
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Rev. 1.3
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Rev. 0.9
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
DESCRIPTION
Original.
Revised
- The test condition of ICC1 and ICC2
- Symbols CE#,OE# and WE# B CE , OE and WE
- The ordering information of package ,STSOP-1 is revised as STSOP.
Revised
- Improve IDR from 20µA to 10µA (LL-version , max.)
- Package outline dimension
Revised
- Add Standby Current ISB1=20µA for special requirement
( LL-version , max. )
- Ordering information in Standby Current column
( maximum typical )
- Standby Current in FEATURES section
Rev.1.1 : 3mA (typical) normal
Rev.1.2 : 0.3mA (typical) normal
- Cycle time condition of ICC2 in DC electrical characteristics
Rev.1.1 : Tcycle=1ms
Rev. 1.2 : Tcycle=1µs
- Waveforms
- Add under/overshoot range of VIL & VIH
Add order information for lead free product
DATE
Apr. 26,2001
May. 14,2001
May 14,2002
May 20,2002
May 15,2003
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80027
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