UT62256CSC-35E 查看數據表（PDF） - Utron Technology Inc
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UT62256CSC-35E Datasheet PDF : 12 Pages
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Rev. 1.0
UTRON
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
Input Capacitance
CIN
-
8
Input/Output Capacitance
CI/O
-
10
Note : These parameters are guaranteed by device characterization, but not production tested.
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = -20℃~80℃)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYMBOL
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
UT62256C(E)-35 UT62256C(E)-70
MIN. MAX. MIN. MAX.
35
-
70
-
-
35
-
70
-
35
-
70
-
25
-
35
10
-
10
-
5
-
5
-
-
25
-
35
-
25
-
35
5
-
5
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT62256C(E)-35 UT62256C(E)-70
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC
35
-
70
-
Address Valid to End of Write
tAW
30
-
60
-
Chip Enable to End of Write
tCW
30
-
60
-
Address Set-up Time
tAS
0
-
0
-
Write Pulse Width
tWP
25
-
50
-
Write Recovery Time
tWR
0
-
0
-
Data to Write Time Overlap
tDW
20
-
30
-
Data Hold from End of Write Time
tDH
0
-
0
-
Output Active from End of Write
tOW*
5
-
5
-
Write to Output in High Z
tWHZ*
-
15
-
25
*These parameters are guaranteed by device characterization, but not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
P80071
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