HFBR-53D3 查看數據表（PDF） - HP => Agilent Technologies
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HFBR-53D3 Datasheet PDF : 16 Pages
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11
LASER
DRIVER
CIRCUIT
PECL
INPUT
C5
0.1 µF
VEET 9
8
TD+
TD- 7
5 V dc
R3 R2
68 68
C9 0.01 µF
C10 0.01 µF
R4 R1
191 191
HFBR/HFCT-53D3
FIBER-OPTIC
TRANSCEIVER
VCCT 6
L2
C2
1 µH
0.1 µF
VCCR 5
C1
L1
+ C8* 1 µH
0.1
10 µF*
µF
50 W
50 W
R13
150
5 V dc
C3 + C4
0.1
10
µF
µF
3.3 V dc
+
GND
VCC2 VEE2
TD+
OUTPUT
DRIVER
TD-
R12
150
CLOCK
SYNTHESIS
CIRCUIT
PARALLEL
TO SERIAL
CIRCUIT
HDMP-1536A/-1546A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
TRANSCEIVER)
SIGNAL
DETECT
CIRCUIT
SD 4
R9
TO SIGNAL DETECT (SD)
INPUT AT UPPER-LEVEL-IC
PRE-
AMPLIFIER
RD- 3
POST-
AMPLIFIER
RD+ 2
VEER 1
270
R11 R10
270 270
C12 0.01 µF
C11 0.01 µF
50 W
R14
100
50 W
RD-
INPUT
BUFFER
RD+
CLOCK
RECOVERY
CIRCUIT
SERIAL TO
PARALLEL
CIRCUIT
SEE HDMP-1536A/-1546A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
NOTES:
*C8 IS AN OPTIONAL BYPASS CAPACITOR FOR ADDITIONAL LOW-FREQUENCY NOISE FILTERING.
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50 W MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50 W TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
Figure 3. Recommended Gigabit/sec Ethernet HFBR/HFCT-53D3 Fiber-Optic Transceiver and HDMP-1536A/1546A
SERDES Integrated Circuit Transceiver Interface and Power Supply Filter Circuits.
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