HD49343HNP 查看數據表（PDF） - Renesas Electronics
零件编号
产品描述 (功能)
生产厂家
HD49343HNP Datasheet PDF : 23 Pages
| |||
HD49343NP/HNP
Preliminary
Electrical Characteristics (cont.)
Items for CDS_in Mode
(Unless otherwise specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V)
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Remarks
Consumption current
IDD1
—
(40)
—
mA fCLK = 36 MHz
HD49343HNP
IDD2
—
(25)
—
mA fCLK = 25 MHz
HD49343NP
CCD offset tolerance range VCCD
(–150)
—
(150)
mV
Sampling timing
specifications
tCDS1
tCDS2
—
Typ 0.8
(1.5)
1/4fCLK
—
ns
Typ 1.2
ns
Refer to table
4
tCDS3
tCDS4
—
Typ 0.8
(1.5)
1/4fCLK
—
ns
Typ 1.2
ns
tCDS5
Typ 0.85
1/2fCLK
Typ 1.0
ns
tCDS6
—
(5)
—
ns
tCDS7
11
—
—
ns
tCDS8
11
—
—
ns
tCDS9
—
(7)
—
ns
tCDS10
—
(16)
—
ns
Clamp level
CLP(00)
—
(56)
—
LSB
Clamp level =
CLP(09)
—
(128)
—
LSB
CLP(31)
—
(304)
—
LSB
settings value
8 + 56
PGA gain at CDS_in
PGA(0)
–8
–6
–4
dB
At 1.0 V input,
PGA(256)
2
4
6
dB
PGA(512)
12
14
16
dB
PGA(768)
22
24
26
dB
PGA(1023)
32
34
36
dB
when PGA
output is 1V, it
is defined as
0dB
Note: Values within parentheses ( ) are for reference.
Items for ADC_in Mode
Item
Symbol
Min
Typ
Consumption current
IDD3
—
(30)
IDD4
—
(20)
Timing specifications
tADC1
tADC2
tADC3
—
Typ 0.85
Typ 0.85
(6)
1/2fADCLK
1/2fADCLK
tADC4
—
(14.5)
tADC5
—
(23.5)
Input current at ADC input IINCIN
–110
—
Clamp level at ADC input OF2
1848
2048
PGA gain at ADC_in
GSL(0)
–8
–6
GSL(128)
–3
–1
GSL(256)
2
4
GSL(384)
7
9
GSL(511)
12
14
Note: Values within parentheses ( ) are for reference.
Max
—
—
—
Typ 1.15
Typ 1.15
—
—
110
2248
–4
1
6
11
16
Unit Test Conditions
Remarks
mA fCLK = 36 MHz
mA fCLK = 25 MHz
ns
ns
ns
ns
ns
A VIN = 1.0 V to 2.0 V
LSB
dB
At 1.0 V input,
dB
when PGA
dB
output is 1V, it
dB
is defined as
0dB
dB
R19DS0068EJ0200 Rev.2.00
Jul 06, 2012
Page 5 of 22
Share Link: 