N25Q128A23EF8H0G 查看數據表（PDF） - Numonyx -> Micron

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N25Q128A23EF8H0G

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Numonyx -> Micron 

Signal descriptions

2

Signal descriptions

N25Q128 - 3 V

2.1

Serial data output (DQ1)

This output signal is used to transfer data serially out of the device. Data are shifted out on

the falling edge of Serial Clock (C). When used as an Input, It is latched on the rising edge

of the Serial Clock (C).

In the Extended SPI protocol, during the Quad and Dual Input Fast Program (QIFP, DIFP)

instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP)

instructions, pin DQ1 is used also as an input.

In the Dual I/O SPI protocol (DIO-SPI) the DQ1 pin always acts as an input/output.

In the Quad I/O SPI protocol (QIO-SPI) the DQ1 pin always acts as an input/output, with the

exception of the Program or Erase cycle performed with the Enhanced Program Supply

Voltage (VPP). In this case the device temporarily goes in Extended SPI protocol. The

protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low.

2.2

Serial data input (DQ0)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C). Data are shifted out on the falling edge of the Serial Clock (C).

In the Extended SPI protocol, during the Quad and Dual Output Fast Read (QOFR, DOFR)

and the Quad and Dual Input/Output Fast Read (QIOFR, DIOFR) instructions, pin DQ0 is

also used as an input/output.

In the DIO-SPI protocol the DQ0 pin always acts as an input/output.

In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of

the Program or Erase cycle performed with the VPP. In this case the device temporarily

goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP

pin voltage goes low.

2.3

Serial Clock (C)

This input signal provides the timing for the serial interface. Instructions, addresses, or data

present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data

are shifted out on the falling edge of the Serial Clock (C).

2.4

Chip Select (S)

When this input signal is high, the device is deselected and serial data output (DQ1) is at

high impedance. Unless an internal program, erase or write status register cycle is in

progress, the device will be in the standby power mode (this is not the deep power-down

mode). Driving Chip Select (S) low enables the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

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