GS82032T-5 查看數據表（PDF） - Giga Semiconductor

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GS82032T-5

64K x 32 2M Synchronous Burst SRAM

Giga Semiconductor 

Preliminary

GS82032T/Q-150/138/133/117/100/66

AC Test Conditions

Parameter

Conditions

Input high level

Input low level

Input slew rate

Input reference level

Output reference level

Output load

2. 3V

0.2 V

1 V/ns

1.25 V

1.25 V

Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.

4. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

Output Load 2

2.5 V

50Ω

30pF*

DQ

225Ω

VT = 1.25 V

* Distributed Test Jig Capacitance

5pF* 225Ω

DC Electrical Characteristics

Parameter

Input Leakage Current

(except mode pins)

ZZ Input Current

Symbol

IIL

IINZZ

Mode Pin Input Current

IINM

Output Leakage Current

IOL

Output High Voltage

VOH

Output High Voltage

VOH

Output Low Voltage

VOL

Test Conditions

VIN = 0 to VDD

VDD ≥ VIN ≥ VIH

0 V ≤ VIN ≤ VIH

VDD ≥ VIN ≥ VIL

0 V ≤ VIN ≤ VIL

Output Disable,

VOUT = 0 to VDD

IOH = –4 mA, VDDQ = 2.375 V

IOH = –4 mA, VDDQ = 3.135 V

IOL = 4 mA

Min

–1 uA

–1 uA

–1 uA

–300 uA

–1 uA

–1 uA

1.7 V

2.4 V

Max

1 uA

1 uA

300 uA

1 uA

1 uA

1 uA

0.4 V

Rev: 1.04 2/2001

11/23

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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