74HCT107D-Q100 查看數據表（PDF） - NXP Semiconductors.

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74HCT107D-Q100

Dual JK flip-flop with reset; negative-edge trigger

NXP Semiconductors. 

NXP Semiconductors

74HC107-Q100; 74HCT107-Q100

Dual JK flip-flop with reset; negative-edge trigger

tW

VI 90 %

negative

pulse

VM

10 %

0V

tf

VI

positive

pulse

tr

90 %

VM

10 %

0V

tW

VM

tr

tf

VM

VI

G

VCC

VO

DUT

RT

VCC

RL S1

CL

open

001aad983

Fig 7.

Test data is given in Table 9.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Test circuit for measuring switching times

Table 9. Test data

Type

Input

VI

tr, tf

74HC107-Q100 VCC

6 ns

74HCT107-Q100 3 V

6 ns

Load

CL

15 pF, 50 pF

15 pF, 50 pF

RL

1 k

1 k

S1 position

tPHL, tPLH

open

open

tPZH, tPHZ

GND

GND

tPZL, tPLZ

VCC

VCC

74HC_HCT107_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 18 November 2013

© NXP B.V. 2013. All rights reserved.

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