74HCT107D-Q100 查看數據表（PDF） - NXP Semiconductors.
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74HCT107D-Q100 Datasheet PDF : 17 Pages
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NXP Semiconductors
74HC107-Q100; 74HCT107-Q100
Dual JK flip-flop with reset; negative-edge trigger
5. Pinning information
5.1 Pinning
+&4
+&74
-
4
4
.
4
4
*1'
9&&
5
&3
.
5
&3
-
DDD
Fig 4. Pin configuration SO14 and TSSOP14
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1J, 2J
1, 8
1Q, 2Q
2, 6
1Q, 2Q
3, 5
1K, 2K
4, 11
1CP, 2CP
12, 9
1R, 2R
13, 10
GND
7
VCC
14
Description
synchronous J input
complement output
true output
synchronous K input
clock input (HIGH-to-LOW edge-triggered)
asynchronous reset input (active LOW)
ground (0 V)
supply voltage
74HC_HCT107_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 November 2013
© NXP B.V. 2013. All rights reserved.
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