LTC1416 查看數據表（PDF） - Linear Technology
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LTC1416 Datasheet PDF : 20 Pages
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LTC1416
POWER REQUIRE E TS The q denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP
MAX
UNITS
ISS
Negative Supply Current
Nap Mode
Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
q
7
10
mA
20
µA
15
µA
PDISS
Power Dissipation
Power Dissipation, Nap Mode
SHDN = 0V, CS = 0V
q
70
100
mW
4
6
mW
Power Dissipation, Sleep Mode
SHDN = 0V, CS = 5V
0.1
mW
WU
TI I G CHARACTERISTICS The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5, see Figures 15 to 21)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
tCONV
tACQ
tACQ+CONV
t1
t2
t3
t4
t5
t6
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Acquisition + Conversion Time
CS to RD Setup Time
CS↓ to CONVST↓ Setup Time
CS↓ to SHDN↓ Setup Time
SHDN↑ to CONVST↓ Wake-Up Time
CONVST Low Time
CONVST to BUSY Delay
(Note 9)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
CS = 0V (Note 10)
(Notes 10, 11)
CL = 25pF
q 400
kHz
q 1.5
1.9
2.2
µs
q
100
400
ns
q
2
2.5
µs
q
0
ns
q 10
ns
q 10
ns
400
ns
q 40
ns
25
ns
q
50
ns
t7
Data Ready Before BUSY↑
(Note 9)
75
100
ns
q 50
ns
t8
Delay Between Conversions
t9
Wait Time RD↓ After BUSY↑
t10
Data Access Time After RD↓
(Note 10)
CL = 25pF
q 40
ns
q –5
ns
15
25
ns
q
35
ns
CL = 100pF
20
35
ns
q
50
ns
t11
Bus Relinquish Time
t12
RD Low Time
t13
CONVST High Time
0°C ≤ TA ≤ 70°C
– 40°C ≤ TA ≤ 85°C
8
20
ns
q
25
ns
q
30
ns
q
t 10
ns
q 40
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended AIN+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 900ns after the
start of the conversion or after BUSY rises.
4
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