NX25F011A 查看數據表（PDF） - NexFlash -> Winbond Electronics
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NX25F011A
NexFlash -> Winbond Electronics
NX25F011A Datasheet PDF : 26 Pages
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NX25F011A
NX25F041A
Table 2. Write Protect Range Sector Selection (Hex)
Write Protect
Range Config. Bits
Write Protected Sectors
WR3 WR2 WR1 WR0 WD=0
00 00
None
0 0 0 1 000 - 01FH
0 0 1 0 000 - 03FH
0 0 1 1 000 - 05FH
0 1 0 0 000 - 07FH
0 1 0 1 000 - 09FH
0 1 1 0 000 - 0BFH
0 1 1 1 000 - 0DFH
1 0 0 0 000 - 0FFH
1 0 0 1 000 - 11FH
1 0 1 0 000 - 13FH
1 0 1 1 000 - 15FH
1 1 0 0 000 - 17FH
1 1 0 1 000 - 19FH
1 1 1 0 000 - 1BFH
11 11
ALL
WD=1(1)
None
x E0 - 1FF/ 7FFH
x C0 - 1FF/ 7FFH
x A0 - 1FF/ 7FFH
x 80 - 1FF/ 7FFH
x 60 - 1FF/ 7FFH
x 40 - 1FF/ 7FFH
x 20 - 1FF/ 7FFH
x 00 - 1FF/ 7FFH
y E0 - 1FF/ 7FFH
y C0 - 1FF/ 7FFH
y A0 - 1FF/ 7FFH
y 80 - 1FF/ 7FFH
y 60 - 1FF/ 7FFH
y 40 - 1FF/ 7FFH
ALL
Note:
1. NX25F011A x=1 y=0 and NX25F041A x=7 Y=6,
HOLD-R/B, HR[1:0]
The Hold-Ready/Busy (HOLD-R/B) bits HR1 and HR0 are
located at bits CF[1:0] of the configuration register. These
two bits select one of four possible functions: no connect,
HOLD input, R/B Output, or R/B Output with open drain. The
factory setting for the pin is “No Connect”. Warning: this pin
is tied low in the Serial Flash Module and must be left as a
no connect (NC) for Serial Flash Module Applications.
HR1 HR0 Pin Configuration
0
0
HOLD input
0
1
No Connect
1
0
R/B Output (Open Drain)
1
1
R/B Output
Configured as a R/B output, the pin can serve as a system
interrupt. When R/B is high, the array is ready to be
programmed. When R/B is low, it is busy programming. If
configured with an open-drain, an external pull-up resistor
should be used.
As a HOLD input, the pin can be used in conjunction with
the CS and SCK pin to suspend a serial command
sequence without resetting the command. This can be
useful if a command is in process and a higher priority
task on the same SPI bus needs to be attended to. To
suspend a command, HOLD must be brought low while
CS and SCK are low. With HOLD low, further data on the
SI pin is ignored (even while SCK is clocked) and the SO
pin goes to a high-impedance state. To resume the
command sequence, HOLD must be brought high when
CS and SCK are low. See timing diagrams.
Status Register Bit Descriptions
The status register provides status of the Flash array’s
Ready/Busy condition (R/B), transfers between the SRAM
and program buffer (TX), Write-Enable/Disable (WE),
and Compare Not Equal (CNE). The register can be read
using the Read Status Register command (Figure 8).
Ready/Busy Status, BUSY
The BUSY status bit is located at bit ST[7] of the status
register. Testing the BUSY bit is one of several ways to
check Ready/Busy status of the array. At power-up the
BUSY bit is reset to 0.
BUSY=1 The memory array is busy programming.
BUSY=0 The memory array is ready for further use.
SRAM and Program Buffer Transfer, TR
The TR status bit is located at bit ST[6] of the status
register. The bit provides status primarily for use during
the Transfer SRAM to Program Buffer command and
Transfer Program Buffer to SRAM command. An active
state 1 indicates a transfer is in process and the SRAM
or Program Buffer is not available for use. The device will
indicate a BUSY state while the TR bit is active. Upon
power up the TR bit resets to 0.
TR=1 SRAM and Program Buffer Transferring.
TR=0 SRAM and Program Buffer Not Transferring.
Write Enable/Disable, WE
The WE status bit is located at bit ST[4] of the status
register. The bit provides write protect status of global Write
Enable and Write Disable commands. Upon power- up the
WE bit resets to 0.
WE=1 Write Enabled, array can be written to.
WE=0 Write Disabled, array can not be written to.
The WE status bit can also be used to determine the state
of the WP (write protect) pin. This can be done by first
issuing the Write Enable Command and then reading the
WE status bit. If the status bit indicates a "0" (write disabled)
then the WP pin is likely held low.
8
NexFlash Technologies, Inc.
PRELIMINARY NXSF014B-0699
06/11/99
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