AS5C2568DJ 查看數據表（PDF） - Austin Semiconductor
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AS5C2568DJ Datasheet PDF : 9 Pages
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Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
Q
255
SRAM
AS5C2568
+5V
480
Q
30 pF
255
+5V
480
5 pF
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates. The
specified value applies with the outputs unloaded, and
f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
6. t HZCE, tHZOE and tHZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
Fig. 1
OUTPUT LOAD
EQUIVALENT
Fig. 2
OUTPUT LOAD
EQUIVALENT
7. At any given temperature and voltage condition, tHZCE
is less than tLZCE, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
Data Retention Current
CONDITIONS
SYMBOL MIN
VDR
2
CE\ > (VCC - 0.2V)
VCC = 2V ICCDR
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 3V
MAX
--
1.0
2.0
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
0
--
tR
tRC
UNITS
V
mA
NOTES
mA
ns
4
ns
4, 11
AS5C2568
Rev. 2.0 12/00
LOW Vcc DATA RETENTION WAVEFORM
VCC
tCDR
CE\
VIH
VIL
1111122222333334444455555666667777788888
DATA RETENTION MODE
4.5V
V > 2V
DR
4.5V
tR
VDR
11111222223333344444555551111666662111112227777732222233388888433433344
111122223333DON’T CARE
1111222233334444UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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