73K324L-28IHF 查看數據表（PDF） - Teridian Semiconductor Corporation
零件编号
产品描述 (功能)
生产厂家
73K324L-28IHF
Teridian Semiconductor Corporation
73K324L-28IHF Datasheet PDF : 30 Pages
| |||
CONTROL REGISTER 0 (continued)
BIT NO.
D6,D5
NAME
Modulation
Type
D7
Modulation
Option
CONDITION
D6 D5
10
00
01
0
1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
DESCRIPTION
QAM
DPSK
FSK
QAM selects 2400 bit/s. DPSK selects 1200 bit/s.
FSK selects V.23 mode.
DPSK selects 600 bit/s.
FSK selects V.21 mode.
CONTROL REGISTER 1
CR1
001
D7
TRANSMIT
PATTERN
1
D6
TRANSMIT
PATTERN
0
BIT NO.
NAME
D1, D0
Test Mode
D2
Reset
D3
CLK Control
(Clock Control)
D5
D4
D3
D2
D1
D0
ENABLE
DETECT
INT.
BYPASS
SCRAMB/
ADD
PH.EQ
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
CONDITION DESCRIPTION
D1 D0
0
0
Selects Normal Operating mode.
0
1
Analog Loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same carrier frequency as the transmitter. To
squelch the TXA pin, transmit enable bit must be low.
Tone Register bit D2 must be zero.
1
0
Selects remote digital loopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD back to
RXD and continues to transmit data carrier at TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control register
bits (CR0, CR1, CR2, CR3 and Tone) are reset to zero
except CR3 bit D2. The output of the clock pin will be set
to the crystal frequency.
0
Selects 11.0592 MHz crystal echo output at CLK pin.
1
Selects 16 X the data rate output at CLK pin in QAM and
DPSK only.
Page: 9 of 30
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
Share Link: