STLC7550TQFP 查看數據表（PDF） - STMicroelectronics

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STLC7550TQFP

LOW POWER LOW VOLTAGE ANALOG FRONT END

STMicroelectronics 

STLC7550

PIN DESCRIPTION (continued)

2 - HOST INTERFACE (10 pins)

2.1 - Data In (DIN)

In Data Mode, the data word is the input of the DAC

channel. In software, the data word is followed by

the control register word.

2.2 - Data Out (DOUT)

In Data Mode, the data word is the ADC conversion

result. In software, the data word is followed by the

register read.

2.3 - Frame Synchronization (FS)

In master mode, the frame synchronization signal

is used to indicate that the device is ready to send

and receive data. The data transfer begins on the

falling edge of the frame-sync signal. The frame-

sync is generated internally and goes low on the

rising edge of SCLK in master mode. In slave mode

the frame is generated externally.

2.4 - Serial Bit Clock (SCLK)

SCLK clocks the digital data into DIN and out of

DOUT during the frame synchronization interval.

The Serial bit clock is generated internally.

2.5 - Reset Function (RESET)

The reset function is to initialize the internal count-

ers and control register. A minimum low pulse of

100ns is required to reset the chip. This reset

function initiates the serial data communications.

The reset function will initialize all the registers to

their default value and will put the device in a

pre-programmed state. After a low-going pulse on

RESET, the device registers will be initialized to

provide an over-sampling ratio equal to 160, the

serial interface will be in data mode, the DAC

attenuation will be set to infinite, the ADC gain will

be set to 0dB, the Differential input mode on the

ADC converter will be selected, and the multiplexor

will be set on the main inputs IN+ and IN-. After a

reset condition, the first frame synchronization cor-

responds to the primary channel.

2.6 - Power Down (PWRDWN)

The Power-Down input powers down the entire

chip (< 50µW). When PWRDWN Pin is taken low,

the device powers down such that the existing

internally programmed state is maintained. When

PWRDWN is driven high, full operation resumes

after 1ms. If the PWRDWN input is not used, it

should be tied to VDD.

2.7 - Hardware Control (HC0, HC1)

These two pins are used for Hardware/Software

Control of the device. The data on HC0 and HC1

will be latched on to the device on the rising edge

of the Frame Synchronization Pulse. If these two

pins are low, Software Control Mode is selected.

When in Software Control Mode, the LSB of the

16-bit word will select the Data Mode (LSB = 0) or

the Control Mode (LSB = 1). Other combinations of

HC0/HC1 are for Hardware Control. These inputs

should be tied low if not used.

2.8 - Master/Slave Control (M/S)

When M/S is high, the device is in master mode

and Fs is generated internally. When M/S is low,

the device is in slave mode and Fs must be

generated externally.

2.9 - Master Clock Mode (MCM)

When MCM is high, XTALIN is provided externally

and must be equal to 36.864MHz. When MCM is low,

XTALIN is provided externally and must be equal to

oversampling frequency : Fs x Over (see Clock Block

Diagram and §4 Modes of Operation).

2.10 - Timeslot Control (TS)

When TS = 0 the data are assigned to the first

16 bits after falling edge of FS (7546 mode) other-

wise the data are bits 17 to 32.

The case M/S = 1 with TS = 1 is reserved for life-test

(transmit gain fixed to 0dB).

3 - CLOCK SIGNALS (2 pins)

Depending on MCM value, these pins have differ-

ent function.

3.1 - MCM = 1 (XTALIN, XTALOUT)

These pins must be tied to external crystal. For the

value of crystal see Functional Description Chapter

Part 3.

3.2 - MCM = 0 (MCLK, XTALOUT)

MCLK Pin must be connected to an external clock.

XTALOUT is not used.

4/17

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