STLC7550TQFP 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
STLC7550TQFP Datasheet PDF : 17 Pages
| |||
STLC7550
FUNCTIONAL DESCRIPTION (continued)
5 - HOST INTERFACE
The Host interface consist of the shift clock,
the frame synchronization signal, the ADC-
channel data output, and the DAC-channel
data input.
Two modes of serial transfer are available :
- First : Software mode for 15-bit transmit data
transfer and 16-bit receive data transfer
- Second : hardware mode for 16-bit data transfer.
Both modes are selected by the Hardware Control
pins (HC0, HC1).
The data to the device, input/output are MSB-first
in 2’s complement format (see Table 2).
When Control Mode is selected, the device will
internally generate an additional Frame Synchroni-
zation Pulse (Secondary Frame Synchronization
Pulse) at the midpoint of the original Frame Period.
If the device is in slave mode the additional frame
sync (secondary frame sync pulse) must be gener-
ated by the processor. The Original Frame Syn-
chronization Pulse will also be referred to as the
Primary Frame Synchronization Pulse.
Table 2 : Mode Selection
HC1
0
0
0
1
HC0
0
0
1
X
LSB
0
1
X
X
Useful Data
15bits
15bits (+16bits reg.)
16bits
16bits (+16bits reg.)
Secondary
FSYNC
No
Yes
No
Yes
Description
Software Mode for Data Transfer only.
Software Mode for Data Transfer + Control Register Transfer.
Hardware Mode for Data Transfer only.
Hardware Mode for Data Transfer + Control Register Transfer.
Figure 7 : Data Mode
Sampling period
FS
SCLK
TxDI
TxDO
HC1, HC0
- - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -
- - D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -
00 or 01
- - D15 D14
- - D15 D14
Figure 8 : Mixed Mode
Sampling Period
1/2 Sampling Period (see Note)
FS
SCLK
TxDI
Data Word Input
Control Word
TxDO
Data Word Output
Register Word
HC1, HC0
1X
01
Note : In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost.
9/17
Share Link: 