SI3454 查看數據表（PDF） - Silicon Laboratories

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SI3454

QUAD IEEE 802.3AT POE PSE CONTROLLER

Silicon Laboratories 

Si3454

Table 1. PSE Port Interface Recommended Operating Conditions1 (Continued)

Parameter

Symbol

Test Condition

Min Typ Max Unit

Classification Mark Specifications

Mark Voltage

Output Voltage Sense

VMARK

IPORT = 0 mA

IPORT = 5 mA

–10

—

—

—

—

V

–7

V

Threshold Voltage

for Power Good Sense

VPGOOD

Measured at VDRAINn to AGND

1

—

3

V

Bias Current of DRAINn Pin

Current Sense

IDRAINn

VDRAINn = 0 V

—

–25

— µA

Sense resistor value

Sense Voltage

at Current Limit

RSENSE

VILIM

1% tolerance

VSENSEn–VKSENSEn

1x Power Mode

VSENSEn–VKSENSEn

2x Power Mode

0.2475 0.25 0.2525 

100 106.25 112.5 mV

200 212.5 225 mV

DC Disconnect

Sense Voltage

VDC_MIN

VSENSEn – VKSENSEn

1.25 1.875 2.5 mV

SENSEn Pin Bias

Current

ISENSE

VSENSEn – AGND

—

–1

— µA

MOSFET Gate Drive

Drive Current

from GATEn Pin (Active)

GATEn pin active

VGATEn = AGND

1x Power Mode

–60 –40 –20 µA

Drive Current

from GATEn Pin (Off)

Voltage Difference Between

any GATEn and AGND Pin

GATEn pin shut off

VGATEn = AGND + 5 V

IGATEn = –1 µA

—

50

10.5 12

— mA

13

V

Notes:

1. Port voltages are referenced with respect to VPWR. All other voltages are referenced with respect to GND. These

specifications apply over the recommended operating voltage and temperature ranges of the device unless noted

otherwise. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and DGND = 0 V, and VPWR at 48 V.

2. For a description of the detailed behavior of VDD UVLO, see “4.2.2. Global Event Register and Global Event COR

(0x02, 0x03)” .

3. Positive values indicate currents flowing into the device; negative currents indicate current flowing out of the device.

6

Rev. 1.1

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