LTC1406 查看數據表（PDF） - Linear Technology
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LTC1406 Datasheet PDF : 16 Pages
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APPLICATIONS INFORMATION
0
–10
–20
–30
–40
–50
–60
THD
–70
2ND HARMONIC
–80
100k
1M
3RD HARMONIC
10M
100M
INPUT FREQUENCY (Hz)
1406 G03
Figure 4. Distortion vs Input Frequency
0
–10
fSAMPLE = 20MHz
fIN1 = 3.500977MHz
–20
fIN2 = 3.598633MHz
–30
–40
–50
–60
–70
–80
–90
–100
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
1406 G05
Figure 5. Intermodulation Distortion Plot
70
60
50
40
30
20
10
0
100k
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G04
Figure 6. Spurious-Free Dynamic Range vs
Input Frequency
LTC1406
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
( ) ( ) IMD
fa ± fb
Amplitude at
= 20 log
fa ± fb
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibel relative to the RMS value of
a full-scale input signal (see Figure 6).
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full-scale input signal. The LTC1406 has been
designed for wide input bandwidth (250MHz), allowing
the ADC to undersample input signals with frequencies
above the converter’s Nyquist frequency. The noise floor
stays very low at high frequencies; S/(N + D) becomes
dominated by distortion at frequencies far beyond Nyquist.
Analog Inputs
The LTC1406 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The AIN+ and AIN–
inputs are sampled at the same time and the ADC will
always convert the difference of [(AIN+) – (AIN–)] indepen-
dent of the common mode voltage. Any unwanted signal
that is common to both inputs will be rejected by the com-
mon mode rejection of the sample-and-hold circuit. The
common mode rejection holds up to extremely high fre-
quencies (see Figure 7).
The inputs can be driven differentially or single-ended. In
differential mode, both inputs are driven ±0.5V out of
phase with each other. In single-ended mode, the nega-
tive input is tied to a fixed voltage and AIN+ is used as the
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