LTC1164-7(Rev0) 查看數據表（PDF） - Linear Technology
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LTC1164-7 Datasheet PDF : 12 Pages
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APPLICATI S I FOR ATIO
Transient Response
INPUT = 1kHz ± 3V
fCLK = 500kHz
fC = 10kHz
VS = ±7.5V
100µs/DIV
Figure 5.
ts
INPUT
90%
50%
td
1164-7 F05
OUTPUT
LTC1164-7
If, for instance, an LTC1164-7 operating with a 100kHz
clock and 1kHz cutoff frequency receives a 98kHz 10mV
input signal, a 2kHz, 143µVRMS alias signal will appear at
its output. When the LTC1164-7 operates with a clock-to-
cutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 11 shows details.
Table 11. Aliasing (fCLK = 100kHz )
INPUT FREQUENCY
(VIN = 1VRMS,
fIN = fCLK ± fOUT)
(kHz)
50:1, fCUTOFF = 2kHz
190 (or 210)
195 (or 205)
196 (or 204)
197(or 203)
198 (or 202)
199.5 (or 200.5)
100:1, fCUTOFF = 1kHz
97 (or 103)
97.5 (or 102.5)
98 (or 102)
98.5 (or 101.5)
99 (or 101)
99.5 (or 100.5)
OUTPUT LEVEL
(Relative to Input,
0dB = 1VRMS)
(dB)
– 76.1
– 51.9
– 36.3
– 18.4
– 3.0
– 0.2
– 74.2
– 53.2
– 36.9
– 19.6
– 5.2
– 0.7
OUTPUT FREQUENCY
(Aliased Frequency
fOUT = ABS [fCLK ± fIN])
(kHz)
10.0
5.0
4.0
3.0
2.0
0.5
3.0
2.5
2.0
1.5
1.0
0.5
10%
tr
RISE
TIME
(tr)
=
0.39
fCUTOFF
±
5%
SETTLING
(TO 1% of
TIME (ts)
OUTPUT)
=
2.2
fCUTOFF
±5%
TIME DELAY (td) = GROUP
(TO 50% OF OUTPUT)
DELAY
≈
1.2
fCUTOFF
Figure 6.
1164-7 F06
Aliasing
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1164-7 case
at 100:1, an input signal whose frequency is in the range
of fCLK ±3%, will be aliased back into the filter’s passband.
VS = ±7.5V
fCLK = 1MHz
fC = 20kHz
(fCLK/fC) = 50:1
5µs/DIV
1164-7 F07
Figure 7. Eye Diagram
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
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