LTC1164-7CJ(Rev0) 查看數據表（PDF） - Linear Technology
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LTC1164-7CJ Datasheet PDF : 12 Pages
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LTC1164-7
TYPICAL PERFOR A CE CHARACTERISTICS
Table 5. Passband Gain and Phase
VS = Single 5V, Ratio = 50:1, TA = 25°C
Table 6. Passband Gain and Phase
VS = Single 5V, Ratio = 100:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 250kHz (Typical Unit)
0.000
1.250
2.500
3.750
5.000
GAIN (dB)
– 0.085
– 0.085
– 0.252
– 1.056
– 3.562
PHASE (DEG)
180.00
71.54
– 37.15
– 146.12
– 255.22
FREQUENCY (kHz)
fCLK = 250kHz (Typical Unit)
0.000
0.625
1.250
1.875
2.500
GAIN (dB)
– 0.283
– 0.283
– 0.799
– 2.143
– 5.271
fCLK = 500kHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
fCLK = 750kHz (Typical Unit)
0.000
3.750
7.500
11.250
15.000
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
– 0.101
– 0.101
– 0.251
– 0.947
– 3.252
– 0.133
– 0.133
– 0.291
– 0.826
– 2.789
– 0.162
– 0.162
– 0.307
– 0.647
– 2.201
180.00
71.39
– 37.38
–146.44
– 256.02
180.00
71.16
– 37.56
– 146.55
– 256.52
180.00
70.89
– 37.78
– 146.67
– 257.06
fCLK = 500kHz (Typical Unit)
0.000
1.250
2.500
3.750
5.000
fCLK = 750kHz (Typical Unit)
0.000
1.875
3.750
5.625
7.500
fCLK = 1MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
– 0.252
– 0.252
– 0.676
– 1.917
– 4.936
– 0.231
– 0.231
– 0.603
– 1.704
– 4.535
– 0.212
– 0.212
– 0.532
– 1.497
– 4.115
PHASE (DEG)
180.00
71.35
– 37.01
– 143.96
– 248.03
180.00
71.28
– 37.16
– 144.46
– 249.40
180.00
70.94
– 37.72
– 145.55
– 251.81
180.00
70.83
– 38.11
– 146.47
– 253.92
PI FU CTIO S
Power Supply Pins (4, 12)
The V+ (pin 4) and the V – (pin 12) should each be
bypassed with a 0.1µF capacitor to an adequate analog
ground. The filter’s power supplies should be isolated
from other digital or high voltage analog supplies. A low
noise linear supply is recommended. Using a switching
power supply will lower the signal-to-noise ratio of the
filter. The supply during power-up should have a slew rate
less than 1V/µs. When V+ is applied before V – and V – is
allowed to go above ground, a signal diode should clamp
V – to prevent latch-up. Figures 2 and 3 show typical
connections for dual and single supply operation.
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.5µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 1k
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
8
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