LTC1164-7(Rev0) 查看數據表（PDF） - Linear Technology
零件编号
产品描述 (功能)
生产厂家
LTC1164-7 Datasheet PDF : 12 Pages
| |||
PI FU CTIO S
Table 7. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ± 2.5V
Single Supply = 12V
Single Supply = 5V
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
VIN
V+
0.1µF
V–
1
14
2
13 0.1µF
3
12
4 LTC1164-7 11
1k
CLOCK SOURCE
5
10 V+
6
9
7
8
GND
+
DIGITAL SUPPLY
VOUT
1164-7 F02
Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1
VIN
V+
10k
10k
1
14
2
13
0.1µF
3
12
4 LTC1164-7 11
1k
5
10
V+
6
9
CLOCK SOURCE
7
8
GND
+
DIGITAL SUPPLY
+
1µF
VOUT
1164-7 F03
Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1
LTC1164-7
and 5 should be biased at 1/2 supply and should be
bypassed to the analog ground plane with at least a 1µF
capacitor (Figure 3). For single 5V operation at the highest
fCLK of 2MHz, pins 3 and 5 should be biased at 2V. This
minimizes passband gain and phase variations.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V +
gives a 50:1 ratio and pin 10 at V – gives a 100:1 ratio. For
single supply operation the ratio is 50:1 when pin 10 is at
V+ and 100:1 when pin 10 is at ground. When pin 10 is not
tied to ground, it should be bypassed to analog ground
with a 0.1µF capacitor. If the DC level at pin 10 is switched
mechanically or electrically at slew rates greater than
1V/µs while the device is operating, a 10k resistor should
be connected between pin 10 and the DC source.
Filter Input Pin (2)
The input pin is connected internally through a 50k resis-
tor tied to the inverting input of an op amp.
Filter Output Pins (9, 6)
Pin 9 is the specified output of the filter; it can typically
source/sink 1mA. Driving coaxial cables or resistive loads
less than 20k will degrade the total harmonic distortion of
the filter. When evaluating the device’s distortion an
output buffer is required. A noninverting buffer, Figure 4,
can be used provided that its input common-mode range
is well within the filter’s output swing. Pin 6 is an interme-
diate filter output providing an unspecified 6th order
lowpass filter. Pin 6 should not be loaded.
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pins 3 and 5 should be connected to the
analog ground plane. For single supply operation, pins 3
–
LT1056
1k +
1164-7 F04
Figure 4. Buffer for Filter Output
9
Share Link: 