FH8065403552500SR3GQ 查看數據表（PDF） - Intel
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FH8065403552500SR3GQ Datasheet PDF : 745 Pages
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C2000 Product Family—Contents
11.7 Memory-Mapped I/O and Software Interface .......................................................215
11.8 System Manageability ......................................................................................215
11.9 Teaming Support .............................................................................................217
11.10 Register Map ...................................................................................................218
12 PCI Express Root Ports (RP).................................................................................. 219
12.1 Signal Descriptions ..........................................................................................220
12.2 Features .........................................................................................................221
12.3 Architectural Overview .....................................................................................222
12.3.1 Atomic Operations (AtomicOps) Routing .................................................223
12.3.2 Reset Warn Technology ........................................................................225
12.3.3 PCI Power Management Capability .........................................................225
12.3.3.1 Device Power Management States (D-States) .........................225
12.3.3.2
12.3.3.3
12.3.3.4
12.3.3.5
ASPM and ASPM Optionality .................................................226
Power Management Event (PME) Signaling .............................226
Beacon and WAKE# Signaling...............................................226
No Soft Reset Bit ................................................................226
12.3.4 PCI Bridge Subsystem Identification Capability ........................................226
12.3.5 Message Signaled Interrupt (MSI) Capability ...........................................227
12.3.6 Advanced Error Reporting (AER) Capability .............................................227
12.3.7 Access Control Services (ACS) Capability ................................................227
12.4 PCI Configuration Process .................................................................................228
12.4.1 I/O Address Transaction Forwarding.......................................................228
12.4.2 Non-Prefetchable Memory-Address Transaction Forwarding .......................229
12.4.3 Prefetchable Memory-Address Transaction Forwarding..............................229
12.4.4 Bus Master Enable (BME) in the Header Command Register ......................230
12.5 Interrupts and Events.......................................................................................231
12.5.1 Hot-Plug Events ..................................................................................232
12.5.2 System Error (SERR) ...........................................................................232
12.6 Power Management..........................................................................................232
12.7 Physical Layer .................................................................................................232
12.7.1 PCI Express Speed Support ..................................................................232
12.7.2 Form Factor Support ............................................................................232
12.8 Configuration of PCI Express Ports and Link Widths ..............................................233
12.8.1 Soft Straps and Bifurcation ...................................................................234
12.8.2 PCI Express Lanes with Various SKUs Design Consideration ......................235
12.8.2.1 SoC PCI Express Lanes Mapping ...........................................236
12.9 PCI Express RAS Features .................................................................................239
12.9.1 Error Detecting, Reporting and Logging ..................................................239
12.9.2 Data Poisoning ....................................................................................240
12.9.3 Link-Level Cyclical Redundancy Code (LCRC)...........................................240
12.9.4 Link Retraining and Recovery ................................................................240
12.9.5 Unsupported Transactions and Unexpected Completions ...........................240
12.9.6 Unconnected Ports...............................................................................240
12.10 Register Maps .................................................................................................241
12.10.1 Registers in Configuration Space ...........................................................242
12.10.2 PCI Capabilities ...................................................................................243
12.10.2.1 PCI Express Capability .........................................................243
12.10.2.2 PCI Power Management Capability ........................................244
12.10.2.3 PCI Bridge Subsystem Vendor ID Capability ...........................244
12.10.2.4 Message Signaled Interrupts (MSI) Capability .........................244
12.10.3 PCI Express Extended Capabilities .........................................................245
12.10.3.1 Advanced Error Reporting (AER) Extended Capability ...............245
12.10.3.2 Access Control Services (ACS) Extended Capability..................245
12.10.3.3 Product-Specific Registers ....................................................245
Intel® Atom™ Processor C2000 Product Family for Microserver
Datasheet
8
January 2016
Order Number: 330061-003US
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