MX25L6445EM2 查看數據表（PDF） - Macronix International
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MX25L6445EM2
Macronix International
MX25L6445EM2 Datasheet PDF : 72 Pages
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MX25L6445E
GENERAL DESCRIPTION
MX25L6445E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in
two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. The MX25L6445E features
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is ena-
bled by CS# input.
MX25L6445E provides high performance read mode, which may latch address and data on both rising and falling
edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the per-
formance may reach direct code execution, the RAM size of the system may be reduced and further saving system
cost.
MX25L6445E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Continuously Program mode and erase command are executed on 4K-byte sector, 32K-
byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L6445E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Additional Protection and Security
Features
Flexible or
Part
Name
Individual block
4K-bit
(or sector) secured OTP
protection
MX25L6445E
V
V
1 I/O Read
(104 MHz)
V
2 I/O Read
(70 MHz)
V
Read Performance
4 I/O Read
(70 MHz)
1 I/O DT
Read
(50 MHz)
V
V
2 I/O DT
Read
(50 MHz)
V
4 I/O DT
Read
(50 MHz)
V
Additional
Features
Part
Name
RES
(command: AB
hex)
MX25L6445E
16 (hex)
REMS
(command: 90
hex)
C2 16 (hex)
Identifier
REMS2
(command: EF
hex)
C2 16 (hex)
REMS4
(command: DF
hex)
C2 16 (hex)
REMS4D
(command: CF
hex)
C2 16 (hex)
RDID
(command: 9F
hex)
C2 20 17 (hex)
P/N: PM1736
REV. 1.8, DEC. 26, 2011
7
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