STW81103 查看數據表（PDF） - STMicroelectronics

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STW81103

Multi-band RF frequency synthesizer with integrated VCOs

STMicroelectronics 

STW81103

List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. VCO A (direct output) closed loop phase noise at 2.775 GHz

(FSTEP=200 kHz; FPFD=200 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. VCO B (direct output) closed loop phase noise at 4.675 GHz

(FSTEP=200 kHz; FPFD=200 kHz; ICP=3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz

(FSTEP=200 kHz; FPFD=400 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz

(FSTEP=200 kHz; FPFD=400 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz

(FSTEP=200 kHz; FPFD=800 kHz; ICP=1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz

(FSTEP=200 kHz; FPFD=800 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. PFD frequency spurs (direct output; FPFD=200 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14. Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA) . . . . . . . . . . . . . . . 17

Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41

Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42

Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43

Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43

Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44

Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44

Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45

Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46

Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 38. Application diagram with external VCO (LO output from STW81103) . . . . . . . . . . . . . . . . 49

Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49

Figure 40. VFQFPN28 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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