73K222BL-IH/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73K222BL-IH/F Datasheet PDF : 26 Pages
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73K222BL
V.22, V.21, Bell 212A, 103 Single-Chip
Modem with Integrated Hybrid
DATA SHEET
CONTROL REGISTER 0 (continued)
CR0
000
D7
MODUL.
OPTION
BIT NO.
D6
0
NAME
D5
D4
D3
D2
TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
MODE 1
MODE 0
CONDITION DESCRIPTION
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
D7 D5 D4 Selects:
D7
Modulation
0 0 X DPSK mode at 1200 bit/s.
Option
1 0 X DPSK mode at 600 bit/s.
0 1 1 FSK Bell 103 mode.
1 1 1 FSK CCITT V.21 mode.
X = Don’t care
CONTROL REGISTER 1
CR1
001
D7
TRANSMIT
PATTERN
1
D6
TRANSMIT
PATTERN
0
D5
ENABLE
DETECT
INTER.
D4
BYPASS
SCRAMB
D3
CLK
CONTROL
D2
RESET
D1
TEST
MODE
1
D0
TEST
MODE
0
BIT NO.
D1, D0
NAME
Test Mode
D2
Reset
D3
CLK Control
(Clock Control)
CONDITION
D1 D0
0
0
0
1
1
0
1
1
0
1
0
1
DESCRIPTION
Selects normal operating mode
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
Selects normal operation.
Resets modem to power-down state. All
control register bits (CR0, CR1, TONE) are reset to
zero. The output of the CLK pin will be set to the
crystal frequency. This bit clears itself.
Selects 11.0592 MHz crystal echo output at CLK pin.
Selects 16 times the data rate, output at CLK pin in
DPSK modes only.
Page: 10 of 26
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.2
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