SN74LS164DR2 查看數據表（PDF） - ON Semiconductor

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SN74LS164DR2

Serial-In Parallel-Out Shift Register

ON Semiconductor 

SN74LS164

AC WAVEFORMS

*The shaded areas indicate when the input is permitted to change for predictable output performance.

I/fmax

tW

1.3 V

1.3 V

1.3 V

CP

tPHL

tPLH

Q

1.3 V

1.3 V

CONDITIONS: MR = H

MR

1.3 V

1.3 V

tW

trec

1.3 V

CP

tPHL

Q

1.3 V

Figure 1. Clock to Output Delays

and Clock Pulse Width

Figure 2. Master Reset Pulse Width,

Master Reset to Output Delay and

Master Reset to Clock Recovery Time

1/fmax

tW

CP

1.3 V

1.3 V

1.3 V

1.3 V

ts(H)

th(H) ts(L)

th(L)

D

*

1.3 V

1.3 V

1.3 V 1.3 V

Q

1.3 V

1.3 V

Figure 3. Data Setup and Hold Times

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