MJW16206 查看數據表（PDF） - Motorola => Freescale
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MJW16206 Datasheet PDF : 10 Pages
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MJW16206
DYNAMIC DESATURATION
DYNAMIC DESATURATION
The SCANSWITCH series of bipolar power transistors are
specifically designed to meet the unique requirements of hor-
izontal deflection circuits in computer monitor applications.
Historically, deflection transistor design was focused on mini-
mizing collector current fall time. While fall time is a valid
figure of merit, a more important indicator of circuit perfor-
mance as scan rates are increased is a new characteristic,
“dynamic desaturation.” In order to assure a linear collector
current ramp, the output transistor must remain in hard satu-
ration during storage time and exhibit a rapid turn–off transi-
tion. A sluggish transition results in serious consequences.
As the saturation voltage of the output transistor increases,
the voltage across the yoke drops. Roll off in the collector
current ramp results in improper beam deflection and distor-
tion of the image at the right edge of the screen. Design
changes have been made in the structure of the SCANS-
WITCH series of devices which minimize the dynamic desa-
turation interval. Dynamic desaturation has been defined in
terms of the time required for the VCE to rise from 1.0 to
5.0 volts (Figures 13 and 14) and typical performance at opti-
mized drive conditions has been specified. Optimization of
device structure results in a linear collector Current ramp, ex-
cellent turn–off switching performance, and significantly low-
er overall power dissipation.
tfi
90% IC(pk)
VCE
IC
VCE = 20 V 10% IC(pk)
0
tsv
0
0% IB
Figure 13. Deflection Simulator Switching
Waveforms From Circuit in Figure 15
5
VCE
4
DYNAMIC DESATURATION TIME
3
IS MEASURED FROM VCE = 1 V
TO VCE = 5 V
2
1
0
tds
TIME (ns)
Figure 14. Definition of Dynamic
Desaturation Measurement
6
Motorola Bipolar Power Transistor Device Data
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