AD621(RevA) 查看數據表（PDF） - Analog Devices
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AD621 Datasheet PDF : 16 Pages
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20
TO 0.01%
15
TO 0.1%
10
5
0
0
5
10
15
20
OUTPUT STEP SIZE – Volts
Figure 24. Settling Time vs. Step Size, Gain = 100
2.0
1.5
+I B
1.0
0.5
0
–I B
–0.5
–1.0
–1.5
–2.0
–125
–75
–25
25
75
TEMPERATURE – °C
125
175
Figure 25. Input Bias Current vs. Temperature
100µV
100
90
AD621
2V
10
0%
Figure 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical
Scale: 100 µV/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div
INPUT
20V p-p
100kΩ
0.1%
G=10
11kΩ
0.1%
G=100
1kΩ
0.1%
10kΩ
1kΩ
10kΩ
1%
10T
1%
VOUT
+VS
2
1
7
G=100
G=10
AD621
6
5
8
4
3
–VS
Figure 28. Settling Time Test Circuit
0PW 0
100
90
VZR 0
100µV
2V
10
0%
0 WFM
20 WFM AQR WARNING
Figure 26. Gain Nonlinearity, G = 100, RL = 10 kΩ,
CL = 0 pF. Vertical Scale: 100 µV/Div = 100 ppm/Div
Horizontal Scale: 2 Volts/Div
REV. A
–9–
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