LTC2314-14 查看數據表（PDF） - Linear Technology

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LTC2314-14

14-Bit, 4.5Msps Serial Sampling ADC in TSOT

Linear Technology 

LTC2314-14

Applications Information

Overview

The LTC2314-14 is a low noise, high speed, 14-bit succes-

sive approximation register (SAR) ADC. The LTC2314-14

operates over a wide supply range (2.7V to 5.25V) and

provides a low drift (20ppm/°C maximum), internal refer-

ence and reference buffer. The internal reference buffer is

automatically configured to a 2.048V span in low supply

range (2.7V to 3.6V) and to a 4.096V span in the high

supply range (4.75V to 5.25V). The LTC2314-14 samples

at a 4.5Msps rate and supports an 87.5MHz data clock.

The LTC2314-14 achieves excellent dynamic performance

(77dB SINAD, 85dB THD) while dissipating only 31mW

from a 5V supply at the 4.5Msps conversion rate.

The LTC2314-14 outputs the conversion data with one

cycle of conversion latency on the SDO pin. The SDO pin

output logic levels are supplied by the dedicated OVDD

supply pin which has a wide supply range (1.71V to 5.25V)

allowing the LTC2314-14 to communicate with 1.8V, 2.5V,

3V or 5V systems.

The LTC2314-14 provides both nap and sleep power-down

modes through serial interface control to reduce power

dissipation during inactive periods.

Serial Interface

The LT2314-14 communicates with microcontrollers, DSPs

and other external circuitry via a 3-wire interface. A falling

CS edge starts a conversion and frames the serial data

transfer. SCK provides the conversion clock for the current

sample and controls the data readout on the SDO pin of

the previous sample. CS transitioning low clocks out the

first leading zero and subsequent SCK falling edges clock

out the remaining data as shown in Figures 5, 6 and 7 for

three different timing schemes. Data is serially output MSB

first through LSB last, followed by trailing zeros if further

SCK falling edges are applied. Figure 5 illustrates that dur-

ing the case where SCK is held low during the acquisition

phase, only one leading zero is output. Figures 6 and 7

illustrate that for the SCK held high during acquisition or

continuous clocking mode two leading zeros are output.

Leading zeros allow the 14-bit data result to be framed

with both leading and trailing zeros for timing and data

verification. Since the rising edge of SCK will be coincident

with the falling edge of CS, delay t2 is the delay to the first

falling edge of SCK, which is simply 0.5 • tSCK. Delays t2

(CS falling edge to SCK leading edge) and t10 (16th falling

SCK edge to CS rising edge) must be observed for Figures

5, 6 and 7 and any timing implementation in order for the

conversion process and data readout to occur correctly.

The user can bring CS high after the 16th falling SCK edge

provided that timing delay t10 is observed. Prematurely

terminating the conversion by bringing CS high before the

16th falling SCK edge plus delay t10 will cause a loss of

conversion data for that sample. The sample-and-hold is

placed in sample mode when CS is brought high. As shown

in Figure 6, a sample rate of 4.5Msps can be achieved on

the LTC2314-14 by using an 87.5MHz SCK data clock

and a minimum acquisition time of 40ns which results in

the minimum throughput time (tTHROUGHPUT) of 222ns.

Note that the maximum throughput of 4.5Msps can only

be achieved with the timing implementation of SCK held

high during acquisition as shown in Figure 6.

The LTC2314-14 also supports a continuous data clock

as shown in Figure 7. With a continuous data clock the

acquisition time period and conversion time period must

be designed as an exact integer number of data clock

periods. Because the minimum acquisition time is not an

exact multiple of the minimum SCK period, the maximum

sample rate for the continuous SCK timing is less than

4.5Msps. For example, a 4.375Msps throughput is achieved

using exactly 20 data clock periods with the maximum

data clock frequency of 87.5MHz. For this particular case,

the acquisition time period and conversion clock period

are designed as 4 data clock periods (TACQ = 45.7ns) and

16data clock periods (TCONV = 182.9ns) respectively,

yielding a throughput time of 228.6ns.

The following table illustrates the maximum throughput

achievable for each of the three timing patterns. Note

that in order to achieve the maximum throughput rate of

4.5Msps, the timing pattern where SCK is held high during

the acquisition time must be used.

Table 1: Maximum Throughput vs Timing Pattern

TIMING PATTERN

MAXIMUM

THROUGHPUT

SCK high during TACQ

SCK low during TACQ

SCK continuous (tTHROUGHPUT = 20 periods)

4.5Msps

4.375Msps

4.375Msps

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For more information www.linear.com/2314-14

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