LTC2314-14 查看數據表（PDF） - Linear Technology

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LTC2314-14

14-Bit, 4.5Msps Serial Sampling ADC in TSOT

Linear Technology 

LTC2314-14

Block Diagram

ANALOG SUPPLY

RANGE 2.7V TO 5.25V

2.2µF

1

VDD

2.5V LDO

2.2µF

DIGITAL SUPPLY

RANGE 1.71V TO 5.25V

5

OVDD

ANALOG

INPUT RANGE

0V TO VREF

AIN

4

+

S/H

–

14-BIT SAR ADC

2.2µF

REF

2

GND

3

2×/4×

1.024V

BANDGAP

TS8 PACKAGE

ALL CAPACITORS UNLESS

NOTED ARE HIGH QUALITY,

CERAMIC CHIP TYPE

THREE-STATE

SERIAL

OUTPUT

PORT

SDO

6

TIMING

LOGIC

SCK

7

CS

8

231414 BD

TIMING DiagramS

16TH EDGE

t8

SCK

OVDD/2

SDO

Hi-Z

Figure 1. SDO Into Hi-Z after 16TH SCK↓

231414 TD01

t7

SCK

OVDD/2

SDO

VIH

VIL

Figure 3. SDO Data Valid Hold after SCK↓

231414 TD03

t9

CS

OVDD/2

SDO

Hi-Z

Figure 2. SDO Into Hi-Z after CS↑

231414 TD02

t4

SCK

OVDD/2

VOH

SDO

VOL

Figure 4. SDO Data Valid Access after SCK↓

231414 TD04

For more information www.linear.com/2314-14

231414f

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