HCPL-0710-060E 查看數據表（PDF） - HP => Agilent Technologies
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HCPL-0710-060E Datasheet PDF : 17 Pages
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Package Characteristics
Parameter
Input-Output Momentary 0710
Withstand Voltage
7710
Resistance
(Input-Output)
Capacitance
(Input-Output)
Input Capacitance
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
-7710
-0710
-7710
-0710
Notes:
1. The LED is ON when VI is low and OFF
when VI is high.
2. tPHL propagation delay is measured from
the 50% level on the falling edge of the VI
signal to the 50% level of the falling edge
of the VO signal. tPLH propagation delay is
measured from the 50% level on the rising
edge of the VI signal to the 50% level of the
rising edge of the VO signal.
3. Mimimum Pulse Width is the shortest
pulse width at which 10% maximum, Pulse
Width Distortion can be guaranteed.
Maximum Data Rate is the inverse of
Minimum Pulse Width. Operating the
HCPL-x710 at data rates above 12.5 MBd is
possible provided PWD and data
dependent jitter increases and relaxed
noise margins are tolerable within the
application. For instance, if the maximum
allowable variation of bit width is 30%, the
maximum data rate becomes 37.5 MBd.
Please note that HCPL-x710 performances
above 12.5 MBd are not guaranteed by
Hewlett-Packard.
Symbol Min. Typ. Max. Units
VISO
3750
3750
Vrms
RI-O
1012
Ω
Test Conditions
RH ≤ 50%,
t = 1 min.,
TA = 25°C
VI-O = 500 Vdc
Fig. Note
8, 9,
10
8
CI-O
0.6
pF
f = 1 MHz
CI
3.0
11
θjci
145
°C/W Thermocouple
160
located at center
θjco
140
135
underside of package
PPD
150 mW
4. PWD is defined as |tPHL - tPLH|.
%PWD (percent pulse width distortion) is
equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst
case difference in tPHL and/or tPLH that will
be seen between units at any given
temperature within the recommended
operating conditions.
6. CMH is the maximum common mode
voltage slew rate that can be sustained
while maintaining VO > 0.8 VDD2. CML is the
maximum common mode voltage slew rate
that can be sustained while maintaining VO
< 0.8 V. The common mode voltage slew
rates apply to both rising and falling
common mode voltage edges.
7. Unloaded dynamic power dissipation is
calculated as follows: CPD * VDD2 * f + IDD *
VDD, where f is switching frequency in
MHz.
8. Device considered a two-terminal device:
pins 1, 2, 3, and 4 shorted together and
pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-
0710 is proof tested by applying an
insulation test voltage ≥4500 VRMS for 1
second (leakage detection current limit, II-O
≤5 µA). Each HCPL-7710 is proof tested by
applying an insulation test voltage ≥ 4500 V
rms for 1 second (leakage detection current
limit, II-O ≤ 5 µA).
10. The Input-Output Momentary Withstand
Voltage is a dielectric voltage rating that
should not be interpreted as an input-output
continuous voltage rating. For the
continuous voltage rating refer to your
equipment level safety specification or
Agilent Application Note 1074 entitled
“Optocoupler Input-Output Endurance
Voltage.”
11. CI is the capacitance measured at pin 2 (VI).
5
0 °C
4
25 °C
85 °C
3
2
1
0
0
1
2
3
4
5
VI (V)
Figure 1. Typical output voltage vs. input
voltage.
7
2.2
0 °C
2.1
25 °C
85 °C
2.0
1.9
1.8
1.7
1.6
4.5
4.75
5
5.25
5.5
VDD1 (V)
Figure 2. Typical input voltage switching
threshold vs. input supply voltage.
29
27
25
TPLH
23
21
TPHL
19
17
15
0 10 20 30 40 50 60 70 80
TA (C)
Figure 3. Typical propagation delays vs.
temperature.
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