LE82Q965SLJAC 查看數據表（PDF） - Intel

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LE82Q965SLJAC

Intel® 965 Express Chipset Family

Intel 

5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 132

5.2.15 C0ODTCTRL—Channel 0 ODT Control ....................................... 134

5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 134

5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 135

5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 135

5.2.19 C1DRB43—Channel 1 DRAM Rank Boundary Address 3 ............... 136

5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 136

5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 137

5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PreCharge ........................ 137

5.2.23 C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 138

5.2.24 C1CYCTRKWR—Channel 1 CYCTRK Write .................................. 139

5.2.25 C1CYCTRKRD—Channel 1 CYCTRK Read ................................... 139

5.2.26 C1CKECTRL—Channel 1 CKE Control ........................................ 140

5.2.27 C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 142

5.2.28 C1ODTCTRL—Channel 1 ODT Control ....................................... 144

5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 145

5.2.30 EPC0DRB1—ME Channel 0 DRAM Rank Boundary Address 1........ 145

5.2.31 EPC0DRB2—ME Channel 0 DRAM Rank Boundary Address 2........ 146

5.2.32 EPC0DRB3—ME Channel 0 DRAM Rank Boundary Address 3........ 146

5.2.33 EPC0DRA01—ME Channel 0 DRAM Rank 0,1 Attribute ................. 147

5.2.34 EPC0DRA23—ME Channel 0 DRAM Rank 2,3 Attribute ................. 147

5.2.35 EPDCYCTRKWRTPRE—MED CYCTRK WRT PRE ............................ 148

5.2.36 EPDCYCTRKWRTACT—MED CYCTRK WRT ACT............................ 148

5.2.37 EPDCYCTRKWRTWR—MED CYCTRK WRT WR ............................. 149

5.2.38 EPDCYCTRKWRTRD—MED CYCTRK WRT READ ........................... 150

5.2.39 EPDCKECONFIGREG—MED CKE Related Configuration Register .... 151

5.2.40 MEMEMSPACE—ME Memory Space configuration ........................ 152

5.2.41 EPDREFCONFIG—ME DRAM Refresh Configuration ...................... 153

5.2.42 TSC1—Thermal Sensor Control 1 ............................................. 154

5.2.43 TSC2—Thermal Sensor Control 2 ............................................. 156

5.2.44 TSS—Thermal Sensor Status................................................... 157

5.2.45 TSTTP—Thermal Sensor Temperature Trip Point......................... 157

5.2.46 TCO—Thermal Calibration Offset.............................................. 158

5.2.47 THERM1—Hardware Protection ................................................ 159

5.2.48 TIS—Thermal Interrupt Status ................................................ 159

5.2.49 TSMICMD—Thermal SMI Command.......................................... 161

5.2.50 PMSTS—Power Management Status ......................................... 161

5.3 MEBAR Registers ................................................................................ 163

5.3.1 EPESD—ME Element Self Description........................................ 163

5.3.2 EPLE1D—Controller Link Entry 1 Description.............................. 164

5.3.3 EPLE1A—Controller Link Entry 1 Address .................................. 164

5.3.4 EPLE2D—Controller Link Entry 2 Description.............................. 165

5.3.5 EPLE2A—Controller Link Entry 2 Address .................................. 166

6

PCI Express* Registers (Device 1, Function 0) (Intel® 82Q965/82G965/82P965 Only)167

6.1 PCI Express* Configuration Register Details (Device 1, Function 0)............ 170

6.1.1 VID1—Vendor Identification .................................................... 170

6.1.2 DID1—Device Identification .................................................... 170

6.1.3 PCICMD1—PCI Command ....................................................... 171

6.1.4 PCISTS1—PCI Status ............................................................. 173

6.1.5 RID1—Revision Identification .................................................. 174

6.1.6 CC1—Class Code ................................................................... 174

6.1.7 CL1—Cache Line Size............................................................. 175

6.1.8 HDR1—Header Type .............................................................. 175

6.1.9 PBUSN1—Primary Bus Number ................................................ 175

6

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