LE82Q965SLJAC 查看數據表（PDF） - Intel

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LE82Q965SLJAC

Intel® 965 Express Chipset Family

Intel 

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

8.2.9

8.2.10

8.2.11

8.2.12

8.2.13

8.2.14

8.2.15

8.2.16

8.2.17

8.2.18

8.2.19

8.2.20

8.2.21

8.2.22

8.2.23

8.2.24

8.2.25

8.2.26

8.2.27

PCISTS2—PCI Status ............................................................. 258

RID2—Revision Identification .................................................. 259

CC—Class Code Register ........................................................ 259

CLS—Cache Line Size............................................................. 260

MLT2—Master Latency Timer................................................... 260

HDR2—Header Type .............................................................. 260

MMADR—Memory Mapped Range Address ................................. 261

SVID2—Subsystem Vendor Identification .................................. 261

SID2—Subsystem Identification .............................................. 262

ROMADR—Video BIOS ROM Base Address ................................. 262

CAPPOINT—Capabilities Pointer ............................................... 263

MINGNT—Minimum Grant ....................................................... 263

MAXLAT—Maximum Latency ................................................... 263

MCAPPTR—Mirror of Device 0 Capabilities Pointer....................... 264

CAPID0—Capability Identifier .................................................. 264

MGGC—Mirror of Device 0 GMCH Graphics Control Register ......... 265

DEVEN—Device Enable........................................................... 266

SSRW—Mirror Function 0 Software Scratch Read/Write............... 267

BSM—Mirror of Function 0 Base of Stolen Memory...................... 267

HSRW—Mirror of Device 2, Function 0 Hardware Scratch Read-Write268

PMCAPID—Mirror Function 0 Power Management Capabilities ID .. 268

PMCAP—Mirror Function 0 Power Management Capabilities .......... 269

PMCS—Power Management Control/Status ................................ 270

SWSMI—Mirror of Function 0 Software SMI ............................... 271

9

Manageability Engine (ME) Subsystem Registers (Device 3, Functions 0,1,2) ......... 273

9.1 Host Embedded Controller Interface (HECI1) Configuration Register Details

(Device 3, Function 0)......................................................................... 273

9.1.1 ID—Identifiers ...................................................................... 274

9.1.2 CMD—Command ................................................................... 274

9.1.3 STS—Device Status ............................................................... 276

9.1.4 RID—Revision ID................................................................... 277

9.1.5 CC—Class Code..................................................................... 277

9.1.6 CLS—Cache Line Size............................................................. 277

9.1.7 MLT—Master Latency Timer .................................................... 278

9.1.8 HTYPE—Header Type ............................................................. 278

9.1.9 HECI_MBAR—HECI MMIO Base Address .................................... 279

9.1.10 SS—Sub System Identifiers .................................................... 279

9.1.11 CAP—Capabilities Pointer........................................................ 280

9.1.12 INTR—Interrupt Information ................................................... 280

9.1.13 MGNT—Minimum Grant .......................................................... 280

9.1.14 MLAT—Maximum Latency ....................................................... 281

9.1.15 HFS—Host Firmware Status .................................................... 281

9.1.16 PID—PCI Power Management Capability ID ............................... 281

9.1.17 PC—PCI Power Management Capabilities................................... 282

9.1.18 PMCS—PCI Power Management Control And Status .................... 283

9.1.19 MID—Message Signaled Interrupt Identifiers ............................. 284

9.1.20 MC—Message Signaled Interrupt Message Control ...................... 284

9.1.21 MA—Message Signaled Interrupt Message Address ..................... 285

9.1.22 MD—Message Signaled Interrupt Message Data ......................... 285

9.1.23 HIDM—HECI Interrupt Delivery Mode ....................................... 286

9.2 HECI2 Configuration Register Details (Device 3, Function 1) ) (Intel® 82Q965

GMCH Only) ...................................................................................... 287

9.2.1 ID—Identifiers ...................................................................... 288

9.2.2 CMD—Command ................................................................... 288

Datasheet

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