IS43TR16256A-093NBL(2016) 查看數據表（PDF） - Integrated Silicon Solution
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IS43TR16256A-093NBL Datasheet PDF : 88 Pages
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IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
2.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET needs
to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10 ns).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
((
((
((
((
((
((
((
((
((
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
)( ()
))
))
))
))
))
))
))
))
))
((
VDD,VDDQ
))
tCKSRX
((
((
((
((
((
((
((
((
))
))
))
))
))
))
))
))
RESET#
CKE
T=100nS
T=5(0(0µS
((
((
))
))
))
tIS
Tmin=10nS
((
((
)( ()
)( ()
))
))
((
((
((
))
))
))
((
((
((
)( ()
)( ()
)( ()
))
))
))
((
((
))
))
((
((
)( ()
)( ()
))
))
tDLLK
((
))
((
)( () Valid
))
((
CMMAND
)( ()
))
((
BA
)( ()
))
((
ODT
)( ()
))
tXPR
tIS
tMRD
tMRD
tMRD
tMOD
tZQinit
((
((
((
((
((
((
((
((
)( ()
1) )( () MRD )( () MRD )( () MRD )( () MRD )( () ZQCL )( ()
1) )( () Valid
))
))
))
))
))
))
))
))
((
((
((
((
((
((
((
((
)( ()
)( () MR2 )( () MR3 )( () MR1 )( () MR0 )( ()
)( ()
)( () Valid
))
))
))
))
))
))
))
))
tIS
tIS
((
((
((
((
)( ()
Stat)(i()c LOW in case RTT_Nom is enabled at time Tg, otherwise static HIG)( H() or LOW )( () Valid
))
))
))
))
RTT
((
((
((
((
((
((
((
((
))
))
))
))
))
))
))
))
Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
( ( Time
) ) Break
Figure2.1.2 Reset Procedure at Power Stable Condition
((
))
DON’T
CARE
2.3 Register Definition
2.3.1 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by
the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command.
As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized
and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers
can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even
if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must
be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which
means these commands can be executed any time after power-up without affecting the array contents The mode register
set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time
required between two MRS commands shown as below.
Integrated Silicon Solution, Inc. – www.issi.com –
9
Rev. G2
07/28/2016
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