MC100LVE222FAR2G 查看數據表（PDF） - ON Semiconductor
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MC100LVE222FAR2G Datasheet PDF : 8 Pages
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MC100LVE222
VCCO
Qb2
Qb2
Qb1
Qb1
Qb0
Qb0
VCCO
Qa1
Qa1
Qa0
Qa0
VCCO
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
21
46
MC100LVE222
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
Figure 1. Pinout Assignment (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK0, CLK0
ECL Differential Input Clock
Qd0 CLK1, CLK1
CLK_Sel
Qd0
MR
Qd1 Qa0:1, Qa0:1
ECL Differential Input Clock
ECL Clock Select
ECL Master Reset
ECL Differential Outputs
Qd1 Qb0:2, Qb0:2
ECL Differential Outputs
Qd2 Qc0:3, Qc0:3
Qd0:5, Qd0:5
Qd2 fseln
ECL Differential Outputs
ECL Differential Outputs
ECL 1 or 2 Select
Qd3 VBB
Reference Voltage Output
Qd3 VCC/VCCO
VEE
Qd4
NC
Positive Supply (VCC = VCCO)
Negative Supply
No Connect
Qd4 Note: All VCC/VCCO, and VEE pins must be
Qd5 externally connected to Power Supply to
Qd5
guarantee proper operation. All VCC/VCCO pins
are internally interconnected.
VCCO
Table 2. FUNCTION TABLE
Input
Function
L
H
MR
CLK_Sel
fseln
Active
CLK0
÷1
Reset
CLK1
÷2
MR
CLK0
CLK0
CLK1
CLK1
CLK_Sel
VBB
fsela
fselb
fselc
fseld
÷1
2
Qa0:1
÷2
Qa0:1
3
4
6
Figure 2. Logic Diagram
Qb0:2
Qb0:2
Qc0:3
Qc0:3
Qd0:5
Qd0:5
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