WM8721L(2004) 查看數據表（PDF） - Wolfson Microelectronics plc

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WM8721L
(Rev.:2004)

Internet Audio DAC with Integrated Headphone Driver

Wolfson Microelectronics plc 

WM8721 / WM8721L

MASTER CLOCK TIMING

MCLK

tXTIL

tXTIH

tXTIY

Production Data

Figure 1 System Clock Timing Requirements

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs

unless otherwise stated.

PARAMETER

SYMBOL

System Clock Timing Information

MCLK System clock pulse width high

tXTIH

MCLK System clock pulse width low

tXTIL

MCLK System clock cycle time

tXTIY

MCLK Duty cycle

TEST CONDITIONS

MIN

18

18

54

40:60

TYP

MAX

UNIT

ns

ns

ns

60:40

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

(Output)

DACLRC

(Output)

DACDAT

tDST

tDL

tDHT

Figure 2 Digital Audio Data Timing - Master Mode

Test Conditions

AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, XTI/MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

Audio Data Input Timing Information

DACLRC propagation delay

tDL

from BCLK falling edge

DACDAT setup time to

tDST

BCLK rising edge

DACDAT hold time from

tDHT

BCLK rising edge

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0

10

ns

10

ns

10

ns

w

PD Rev 4.0 November 2004

8

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