73K321L 查看數據表（PDF） - TDK Corporation
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73K321L Datasheet PDF : 24 Pages
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73K321L
CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
GND
VDD
PLCC/DIP
PIN NUMBER
28
15
VREF
26
ISET
24
TYPE DESCRIPTION
I
System Ground.
I
Power supply input, 5V ±10%. Bypass with 0.1 and 22 µF capacitors
to GND.
O
An internally generated reference voltage. Bypass with 0.1 µF
capacitor to GND.
I
Chip current reference. Sets bias current for op-amps. The chip
current is set by connecting this pin to VDD through a 2 MΩ resistor.
ISET should be bypassed to GND with a 0.1µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE
ALE
AD0-AD7
CS
CLK
INT
RD
RESET
12
4-11
20
1
17
14
25
I
Address latch enable. The falling edge of ALE latches the address on
AD0-AD2 and the chip select on CS.
I/O Address/data bus. These bidirectional tri-state multi-plexed lines carry
information to and from the internal registers.
I
Chip select. A low during the falling edge of ALE on this pin allows a
read cycle or a write cycle to occur. AD0-AD7 will not be driven and
no registers will be written if CS (latched) is not active. The state of
CS is latched on the falling edge of ALE.
O
Output clock. This pin is the output of the crystal oscillator frequency
only in the 73K321.
O
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor must then
read the detect register to determine which detect triggered the
interrupt. INT will stay low until the processor reads the detect register
or does a full reset.
I
Read. A low requests a read of the 73K321L internal registers. Data
cannot be output unless both RD and the latched CS are active or
low.
I
Reset. An active high signal high on this pin will put the chip into an
inactive state. All control register bits (CR0, CR1, Tone) will be reset.
The output of the CLK pin will be set to the crystal frequency. An
internal pull down resistor permits power on reset using a capacitor to
VDD.
3
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