BUK106-50L 查看數據表（PDF） - Philips Electronics
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BUK106-50L Datasheet PDF : 14 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK106-50L/S
BUK106-50LP/SP
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.22. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IPS / mA
1.0
BUK106-50L/S
0.5
0
0
2
4
6
8
10
12
14
VPS / V
Fig.23. Typical DC protection supply characteristics.
IPS = f(VPS); normal or overload operation; Tj = 25 ˚C
IISL / mA
150
100
50
VPS / V = 11
BUK106-50L/S
10
9
8
7
6
5
4
0
0
2
4
6
8
10
VIS / V
Fig.24. Typical latched input characteristics, 25 ˚C.
IISL = f(VIS); after overload protection latched
IS / A
200
BUK106-50L/S
150
100
50
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VSD / V
Fig.25. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80 100 120 140
Tmb / C
Fig.26. Normalised limiting clamping energy.
EDSM% = f(Tmb); conditions: ID = 27 A
VDS
0
ID
0
VIS
0
V(CL)DSR
VDD
L
+ VDD
RF
RI = RIS
+ VPS
P
F
P
I
VDS
D
TOPFET
D.U.T.
S
-
R 01
shunt
-ID/100
Fig.27. Clamping energy test circuit, RIS = 100 Ω.
EDSM = 0.5 ⋅ L ID2 ⋅ V(CL)DSR/(V(CL)DSR − VDD)
February 1993
10
Rev 1.200
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