TSB80C186EA13 查看數據表（PDF） - Intel

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TSB80C186EA13

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Intel 

80C186EC 188EC 80L186EC 188EC

272434 – 2

NOTE

1 The LC network is only required when using a third overtone crystal

Figure 2 80C186EC Clock Connections

80C186EC PERIPHERAL

ARCHITECTURE

The 80C186EC integrates several common system

peripherals with a CPU core to create a compact yet

powerful system The integrated peripherals are de-

signed to be flexbile and provide logical interconnec-

tions between supporting units (e g the DMA unit

can accept requests from the Serial Communica-

tions Unit)

The list of integrated peripherals includes

Two cascaded 8259A compatible Programma-

ble Interrupt Controllers

3-Channel Timer Counter Unit

2-Channel Serial Communications Unit

4-Channel DMA Unit

10-Output Chip-Select Unit

32-bit Watchdog Timer Unit

I O Port Unit

Refresh Control Unit

Power Management Unit

The registers associated with each integrated pe-

ripheral are contained within a 128 x 16-bit register

file called the Peripheral Control Block (PCB) The

base address of the PCB is programmable and can

be located on any 256 byte address boundary in ei-

ther memory or I O space

Figure 3 provides a list of the registers associated

with the PCB The Register Bit Summary individually

lists all of the registers and identifies each of their

programming attributes

5

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