BR24C01A-W 查看數據表（PDF） - ROHM Semiconductor
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BR24C01A-W Datasheet PDF : 13 Pages
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Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(10) Random read cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
W
S
T
R
T
R
S
A
I
A
E
T
R
SLAVE
T
WORD
R
SLAVE A
O
T
ADDRESS E
ADDRESS(n)
T
ADDRESS D
DATA(n)
P
SDA
LINE
1 0 1 0 A2 A1 A0
∗
WA
6
WA
0
1 0 1 0 A2 A1A0
D7
D0
RA
A
RA
A
/C
C
/C
C
WK
K
WK
K
Fig.13
BR24C02-W / F-W / FJ-W / FV-W
S
W
S
T
R
T
R
S
A
I
A
E
T
R
SLAVE
T
WORD
R
SLAVE A
O
T
ADDRESS E
ADDRESS(n)
T
ADDRESS D
DATA(n)
P
SDA
LINE
1 0 1 0 A2 A1A0
WA
7
WA
0
1 0 1 0 A2 A1 A0
D7
D0
RA
A
RA
A
/C
C
/C
C
WK
K
WK
K
Fig.14
BR24C04-W / F-W / FJ-W / FV-W
S
W
S
T
R
T
R
S
A
I
A
E
T
R
SLAVE
T
WORD
R
SLAVE A
O
T
ADDRESS E
ADDRESS(n)
T
ADDRESS D
DATA(n)
P
SDA
LINE
1 0 1 0 A2 A1PS
WA
7
WA
0
1 0 1 0 A2 A1PS
D7
D0
RA
A
RA
A
/C
C
/C
C
WK
K
WK
K
Fig.15
• This command can read the designated word address data.
• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words all read enabled]
(See Fig.16 to 18 for the sequential read cycles.)
• This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) by raising SCL to HIGH.
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