AM28F512 查看數據表（PDF） - Advanced Micro Devices
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AM28F512 Datasheet PDF : 35 Pages
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write cycles, the command register internally latches
address and data needed for the programming and
erase operations. For system design simplification, the
Am28F512 is designed to support either WE# or CE#
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE# or CE#
whichever occurs last. Data is latched on the rising edge
of WE# or CE# whichever occurs first. To simplify the fol-
lowing discussion, the WE# pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the WE# signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F512 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM
programming mechanism of hot electron injection.
BLOCK DIAGRAM
VCC
VSS
VPP
WE#
State
Control
Erase
Voltage
Switch
To Array
DQ0–DQ7
Input/Output
Buffers
CE#
OE#
Command
Register
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Data
Latch
Low VCC
Detector
A0–A15
Program/Erase
Pulse Timer
Y-Decoder
Address
Latch
X-Decoder
Y-Gating
524,288
Bit
Cell Matrix
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options (VCC = 5.0 V ± 10%)
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
11561G-1
Am28F512
-70
-90
-120
-150
-200
70
90
120
150
200
70
90
120
150
200
35
35
50
55
55
2
Am28F512
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