BUK101-50GL 查看數據表（PDF） - Philips Electronics
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BUK101-50GL Datasheet PDF : 11 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK101-50GL
Energy & Time
1
BUK101-50GL
Time / ms
0.5
Energy / J
Tj(TO)
0
-60 -20
20
60 100 140 180 220
Tmb / C
Fig.14. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ
ID / A
30
BUK101-50GL
20
typ.
10
0
50
60
70
VIS / V
Fig.15. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
II / uA
500
BUK101-50GL
400
Tj = 25 C
300
200
150 C
100
0
0
2
4
6
8
10
VIS / V
Fig.17. Typical DC input characteristics.
II = f(VIS); normal operation; parameter: Tj
IISL / mA
3
2
PROTECTION LATCHED
BUK101-50GL
RESET
1
NORMAL
0
0
2
4
6
8
VIS / V
Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
IISL = f(VIS); overload protection operated ⇒ ID = 0 A
IS / A
100
BUK101-50GL
50
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.16. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
0
0
Fig.19.
1
2
VSD / V
Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V
January 1993
7
Rev 2.600
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