BUK101-50GL 查看數據表（PDF） - Philips Electronics
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BUK101-50GL Datasheet PDF : 11 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK101-50GL
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.20. Test circuit for resistive load switching times.
VDD = VCL
LD
t p : adjust for correct ID
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.23. Test circuit for inductive load switching times.
RESISTIVE TURN-ON
15
BUK101-50GL
VDS / V
10 td on
tr
90%
5
ID / A
VIS / V
10%
0
0
10
20
30
40
50
time / us
Fig.21. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
15 RESISTIVE TURN-OFF
BUK101-50GL
10
ID / A
5
VIS / V
td off
90%
VDS / V
tf
90%
10%
0
0
5
10
15
20
time / us
Fig.22. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
INDUCTIVE TURN-ON
15
BUK101-50GL
10
tr
td on
5
90%
ID / A
VIS / V
10%
0
VDS / V
0
10
20
30
40
50
time / us
Fig.24. Typical switching waveforms, inductive load.
VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C.
INDUCTIVE TURN-OFF
15
BUK101-50GL
VDS / V
10
td off
tf
5
90%
90%
VIS / V
ID / A
10%
0
0
5
10
15
20
time / us
Fig.25. Typical switching waveforms, inductive load.
VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C.
January 1993
8
Rev 2.600
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