N80L186EB13 查看數據表（PDF） - Intel

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N80L186EB13

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Intel 

80C186EB 80C188EB 80L186EB 80L188EB

AC SPECIFICATIONS

AC Characteristics 80C186EB25 (Continued)

Symbol

Parameter

SYNCHRONOUS INPUTS

TCHIS

TCHIH

TCLIS

TCLIH

TCLIS

TCLIH

TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7

TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0

AD15 0 (AD7 0) READY

READY AD15 0 (AD7 0)

HOLD PEREQ ERROR

HOLD PEREQ ERROR

NOTES

1 See AC Timing Waveforms for waveforms and definition

2 Measure at VIH for high time VIL for low time

3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL

4 Specified for a 50 pF load see Figure 13 for capacitive derating information

5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF

6 See Figure 14 for rise and fall times

7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release

8 TCHOV2 applies to RD and WR only after a HOLD release

9 Setup and Hold are required to guarantee recognition

10 Setup and Hold are required for proper operation

25 MHz

Units Notes

Min Max

10

ns 1 9

3

ns 1 9

10

ns 1 10

3

ns 1 10

10

ns 1 9

3

ns 1 9

29

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