SST39VF1601C 查看數據表（PDF） - Microchip Technology

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SST39VF1601C

16 Mbit (x16) Multi-Purpose Flash Plus

Microchip Technology 

A Microchip Technology Company

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

Data Sheet

Data Protection

The SST39VF1601C/1602C provide both hardware and software features to protect nonvolatile data

from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST39VF1602C supports top hardware block protection, which protects the top 8 KWord block of

the device. The SST39VF1601C supports bottom hardware block protection, which protects the bot-

tom 8KWord block of the device. The Boot Block address ranges are described in Table 4. Program

and Erase operations are prevented on the 8 KWord when WP# is low. If WP# is left floating, it is inter-

nally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase

operations on that block.

Table 4: Boot Block Address Ranges

Product

Bottom Boot Block

SST39VF1601C

Top Boot Block

SST39VF1602C

Address Range

00000H - 01FFFH

FE000H - FFFFFH

T4.0 25018

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#

pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When

no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#

is driven high before a valid Read can take place (see Figure 18).

The Erase or Program operation that has been interrupted needs to be re-initiated after the device

resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF1601C/1602C provide the JEDEC approved Software Data Protection scheme for all

data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of

the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, pro-

viding optimal protection from inadvertent Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are

shipped with the Software Data Protection permanently enabled. See Table 7 for the specific software

©2011 Silicon Storage Technology, Inc.

11

DS-25018A

05/11

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