AD5232BRU10-REEL7_01 查看數據表（PDF） - Analog Devices
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AD5232BRU10-REEL7_01 Datasheet PDF : 20 Pages
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AD5232
USING ADDITIONAL INTERNAL NONVOLATILE EEMEM
The AD5232 contains additional internal user storage registers
(EEMEM) for saving constants and other 8-bit data. Table IV
provides an address map of the internal nonvolatile storage
registers shown in the functional block diagram as EEMEM1,
EEMEM2, and bytes of USER EEMEM.
Table IV. EEMEM Address Map
EEMEM
Address
(ADDR)
EEMEM Contents of Each
Device EEMEM (ADDR)
AD5232 (8B)
0000
0001
0010
0011
0100
0101
***
1111
RDAC1
RDAC2
USER 1
USER 2
USER 3
USER 4
***
USER 14
NOTES
1RDAC data stored in EEMEM locations are transferred to their
corresponding RDAC REGISTER at Power ON, or when
instructions Inst#1 and Inst#8 are executed.
2USER <data> is internal nonvolatile EEMEM registers available
to store and retrieve constants using Inst#3 and Inst#9 respectively.
3AD5232 EEMEM locations are 1 byte each (8 bits).
4Execution of instruction #1 leaves the device in the Read Mode power con-
sumption state. After the last Instruction #1 is executed, the user should
perform a NOP, Instruction #0 com mand to return the device to the low
power idle state.
Table V. RDAC and Digital Register Address Map
Register Address Name of Register*
(ADDR)
AD5232 (8B)
0000
0001
RDAC1
RDAC2
*RDACx registers contain data determining the
position of the variable resistor wiper.
TERMINAL VOLTAGE OPERATING RANGE
The digital potentiometer’s positive VDD and negative VSS power
supply defines the boundary conditions for proper three-terminal
programmable resistance operation. Signals present on terminals
A, B, W that exceed VDD or VSS will be clamped by a forward
biased diode; see Figure 8.
The ground pin of the AD5232 device is primarily used as a
digital ground reference, which needs to be tied to the PCBs’
common ground. The digital input logic signals to the AD5232
must be referenced to the devices’ ground pin (GND), and
satisfy the logic minimum input high level and the maximum
low level defined in the specification table of this data sheet.
An internal level-shift circuit between the digital interface and
the wiper switch control ensures that the common-mode voltage
range of the three-terminals A, W, and B extends from VSS to VDD.
VDD
A
W
B
VSS
Figure 8. Maximum Terminal Voltages Set by VDD and VSS
DETAIL POTENTIOMETER OPERATION
The actual structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The patent-pending
RDAC contains multiple strings of connected resistor segments,
with an array of analog switches that act as the wiper connection
to several points along the resistor array. The number of points
is the resolution of the device. For example, the AD5232 has
256 connection points allowing it to provide better than 0.5%
setability resolution. Figure 9 provides an equivalent dia-
gram of the connections between the three terminals that
make up one channel of the RDAC. The SWA and SWB will
always be ON, while one of the switches SW(0) to SW(2N–1)
will be ON one at a time depending upon the resistance step
decoded from the Data Bits. The resistance contributed by RW
must be accounted for in the output resistance. The SWA and
SWB will always be ON while one of the switches SW(0) to
SW(2N–1) will be ON one at a time, depending upon the
resistance step decoded from the Data Bits. The resistance
contributed by RW must be accounted for in the output resistance.
SWA
AX
SW(2N – 1)
RDAC
WIPER
REGISTER
AND
DECODER
RS SW(2N – 2) WX
RS
SW(1)
RS
SW(0)
RS = RAB / 2N
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
SWB
BX
Figure 9. Equivalent RDAC Structure (Patent Pending)
REV. 0
–11–
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